The Ministry of Electronics and Information Technology (MeitY) plans to train over 85,000 engineers on chip design by expanding the infrastructure available for the technology to 120 academic institutions across the country in the next five years.

Of late, MeitY had conducted a pilot deployment in 2021 under special manpower development programme for Chips to System Design (SMDP-C2SD), wherein a centralised design facility at state-run C-DAC was enabled for remote access by over 50,000 engineering students at 60 academic institutions for designing chips.

To this end, for making available the chip design infrastructure at India Chip Centre of C-DAC, leading industry vendors from EDA (Electronic Design Automation), Electronic Computer-Aided Design (ECAD), IP Core and Design solutions Industry are being partnered with.